1. Technical Field
The present disclosure concerns a differential to single-ended conversion circuit and a multi-stage comparator using the circuit.
2. Description of the Related Art
A known multi-stage comparator, made in MOS (Metal Oxide Semiconductor) or CMOS (Complementary MOS) integrated technology comprises a sequence of differential operational stages continuously decoupled from each other through capacitors. Each stage can be placed in reset, i.e. taken into the closed loop stage, through suitable switches. The operation of the comparator is articulated in two very distinct steps.
In the reset step, the operational stages are reset so as to reach the best bias condition: the terminals of the decoupling capacitors are forced to a common mode voltage dependent upon the topology of the operational elements. This step, amongst other things, allows the offset voltages of the operational elements themselves to be stored in the decoupling capacitors so as to carry out the well known auto-zero procedure.
At the end of the reset step the switches are opened and the operational elements can become offset through the signal present in input: each stage, through the decoupling capacitors, reads the variation of the outputs of the previous stage.
The output of the comparator is a logic signal: therefore the differential information of the last operational stage is converted into single-ended information.
The preferred solution in the prior art is that of introducing a single-ended operational, also continuously decoupled from the previous stage and equipped with its own reset switches, made through MOSFET (MOS Field Effect Transistor) devices.